Single-electron tunnelling logic device

ABSTRACT

A stable output can be obtained with respect to the input level fluctuations. Two impedance elements 1 and 2 each having a single-electron tunnel junction are connected in series. The tunnel resistances R1 and R2 and the junction capacitances C1 and C2 of the respective impedance elements 1 and 2 are determined as R1&gt;R2 and C1&gt;/=C2 or R1&lt;R2 and C1&gt;/=C2. By this, the charge stored on the island portion 4 can be quantized at a roughly integral value times the prime charge e according to the input voltage, the current-voltage characteristics represent Coulomb staircase, a square-shaped Coulomb oscillation characteristics can be obtained, and a constant output current value to an input voltage range with constant width can be obtained, so that it is possible to widen the voltage margin corresponding to the respective input logical level. A stable output can be obtained against the input voltage fluctuations.

DETAILED DESCRIPTION OF THE INVENTION

1. Field of Industrial Utilization

The present invention relates to a logic device, to which asingle-electron tunnelling phenomenon is applied on the basis of Coulombblockade.

2. Prior Art

Recently, various researches for the single-electron tunnellingphenomena observed in tunnel junctions having micro-capacitances havebeen performed extensively. By making the best use of thesingle-electron tunnelling, it is possible to realize a deviceextraordinarily high in speed and extraordinarily low in powerconsumption, in comparison with the conventional microscopic electrondevices. Therefore, the single-electron tunnelling devices are now beingstudied anywhere for actualization.

The origin of the single-electron tunnelling can be summarized asfollows: in the case of a tunnel junction having an extraordinary smallcapacitance, change in charging energy due to the tunnelling of a singleelectron through the junction is not negligible in comparison with theenergy of thermal fluctuation k_(B) T where T is absolute temperatureand k_(B) is Bolzmann's constant. Under these circumferences, an energyloss caused by a single-electron tunnelling must be inhibited. This isreferred to as Coulomb blockade, which is the basic concept of thesingle electron tunnelling phenomena.

The basic unit of the single-electron tunnelling device using theCoulomb blockade characteristics is a three-terminal device composed ofa double-tunnel junction structure obtained by connecting two tunneljunctions in series and a gate electrode connected to a middle electrodebetween these two tunnel junctions, the type of which is referred to assingle-electron tunnelling transistor (SET), in particular. FIG. 15shows the structure of this single-electron tunnelling transistor, inwhich the reference numerals 51 and 52 denote two tunnel junctionportions connected in series. One end of the transistor is referred toas a source electrode portion 55, the other end thereof is referred toas a drain electrode portion 56. Further, a gate electrode 57 isconnected to the middle electrode (island) portion 54 via a capacitor53. When a predetermined bias voltage V_(SD) (=V_(S) -V_(D)) is appliedbetween the source and drain electrode portions 55 and 56 and further avoltage V_(g) is applied to the gate electrode portion 57, it ispossible to obtain linear characteristics between the bias voltageV_(SD) and the channel current I flowing between the source and drainportions 55 and 56, which has a certain gap as shown in FIG. 16. The SETas described above is provided with roughly a linear current-voltage(I-V_(SD)) characteristics when the current I exceeds this gap.Therefore, when the voltage V_(g) applied to the gate electrode 57 ischanged as shown in FIG. 16, it is possible to control the voltage(Coulomb blockade voltage) at which the current I begins to flow.Further, FIG. 17 shows the current I obtained when the gate voltage V₉is changed by keeping the bias voltage V_(SD) equal to a constant valueV_(b). As shown in FIG. 17, the current I oscillates at a period e/C_(g)according to the gate voltage V_(g). This phenomenon is referred to asCoulomb oscillation. By best use of this Coulomb oscillation, it ispossible to use the SET as shown in FIG. 15 as a switching device. Inother words, the current value within the range I≧I_(H) is determined asa high level output H_(out) and the current value within the rangeI≦I_(L) is determined as a low level output L_(out), and thecorresponding ranges of the gate bias V_(g) are determined as the highlevel input H_(in) and low level input L_(in), respectively. Asunderstood with reference to FIG. 17, it is desirable to determine thedifference between I_(H) and I_(L) as large as possible, in order todistinguish the high level H_(out) from the low level L_(out) or viceversa. In this case, however, the input margin is reduced inversely tothat extent. As a result, there exists a possibility that the high leveloutput H_(out) is changed to the low level output L_(out) or vice versaby only a slight change of the input level, because the change betweenthe I_(min) and I_(max) occurs steeply. As a result, there exists aproblem in that this causes an erroneous operation of the SET.

With these problems in mind, therefore, the object of the presentinvention is to provide a single-electron tunnelling logic device, bywhich a stable output can be obtained when an input level fluctuates, byutilizing the best use of the double-tunnel junction characteristics.

In particular, the object of the present invention is to provide asingle-electron tunnelling logic device including double-tunneljunctions, which can obtain Coulomb staircase as the current-voltagecharacteristics, by adjusting the time constants on the basis of thejunction parameters of the tunnel junction portions and further byquantizing the charge accumulated at the island portion to roughlyinteger-time values of the prime charge e according to the inputvoltage.

Further, the object of the present invention is to provide asingle-electron tunnelling logic device having double-tunnel junctionstructure, in which the time constant of the tunnel junction portions ofthe active circuit itself is adjusted to obtain the Coulomb staircase.

Further, the object of the present invention is to provide asingle-electron tunnelling logic device, in which the time constant ofthe tunnel junction portions of the circuit is adjusted by providing acircuit having another tunnel junction portion as charge accumulatingmeans at the gate input portion of the active circuit.

Further, the object of the present invention is to provide asingle-element tunnelling logic device, in which the charge accumulationcontrol circuit is formed by a double-tunnel junction circuit.

Means for Solving the Problems

A single-electron tunnelling logic device according to the presentinvention comprises: a double-tunnel junction portion formed byconnecting first and second single-electron tunnel junctions in series,a bias voltage being applied to both ends thereof; and a signal inputportion connected to a common junction portion between said first andsecond single-electron tunnel junction portions via a capacitanceelement, wherein charge accumulated at the common junction portion isquantized approximately in integer-time unit of a prime charge accordingto the bias voltage.

Here, in said double-tunnel junction portion, a tunnel resistanceR_(T).sup.(i) and a junction capacitance C_(i) of the i-th (i=1, 2)single-electron tunnel junction are so determined that any one of thefollowing conditions can be satisfied:

    R.sub.T.sup.(1) >R.sub.T.sup.(2), C.sub.1 ≧C.sub.2  (i)

    R.sub.T.sup.(2) >R.sub.T.sup.(1), C.sub.2 ≧C.sub.1  (ii)

Further, a single-electron tunnelling logic device according to thepresent invention comprises: a double-tunnel junction portion formed byconnecting first and second single-electron tunnel junctions in series,a bias voltage being applied to both ends thereof; and a signal inputportion connected to a common junction portion between said first andsecond single-electron tunnel junction portions via a capacitanceelement, wherein charge accumulated at another common junction portionbetween said signal input portion and the capacitance device isquantized approximately in integer-time unit of a prime charge accordingto an input voltage applied to said signal input portion.

Here, said signal input portion is a circuit formed by connecting firstand second impedance elements in series, and further the common junctionportion between the first and second impedance elements is connected tothe capacitance element.

Further, at least one of the first and second impedance elements can beformed by a single-electron tunnel junction.

Further, the first and second impedance elements can be both formed by asingle-electron tunnel junction, respectively, and these twosingle-electron tunnel junctions allowed to be different from each otherin at least one of tunnel resistance and junction capacitance thereof.

Further, a plurality of the capacitance elements and a plurality of saidsignal input portions can be connected to the common junction portionbetween said first and second single-electron tunnel junctions.

Further, it is preferable that a tunnel resistance R_(T).sup.(1) and ajunction capacitance C₁ of the first impedance element and a tunnelresistance R_(T).sup.(2) and a junction capacitance C₂ of the secondimpedance element are so determined that any one of the followingconditions can be satisfied:

    R.sub.T.sup.(1) C.sub.1 >R.sub.T.sup.(2) C.sub.2,          (i)

    R.sub.T.sup.(1) C.sub.1 <R.sub.T.sup.(2) C.sub.2,          (ii)

Further, it is preferable that any one of the following conditions canbe satisfied:

    R.sub.T.sup.(1) >R.sub.T.sup.(2), C.sup.1 ≧C.sub.2, (i)

    R.sub.T.sup.(1) <R.sub.T.sup.(2), C.sup.1 ≦C.sub.2, (ii)

Functions

According to the present invention, since the charge accumulated at theisland is controlled in such a way that the output currentcharacteristics with respect to the input voltage applied to the gatecircuit are of Coulomb staircase, square waveform characteristics can beobtained as the output current characteristics (Coulomb oscillationcharacteristics) with respect to the input signal voltage, so that aconstant output current value can be obtained with respect to a constantvoltage width of the input signal. As a result, the margin of thevoltage with respect to the respective input logic levels can bewidened. Consequently, it is possible to obtain a stable output withrespect to the input voltage fluctuations, by effectively unitizing thedouble-tunnel junction characteristics.

Further, in the Coulomb oscillation characteristics, even if the outputcurrent values corresponding to the respective high-level output and thelow-level output and the difference between the two are changed so as tobe increased as much as possible, since the input voltage width can bemaintained at a constant width, it is possible to widen the differencebetween the high-level output and the low-level output, without reducingthe margin of the voltage value with respect to the input logicallevels.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the structure of the double-tunneljunction single-electron transistor (A-SET) related to the firstembodiment of the present invention;

FIG. 2 is a graphical representation showing the I-V_(SD)characteristics with the gate bias as parameters, in which the tunnelresistances R₁ and R₂ and the junction capacitances C₁ and C₂ of the twotunnel junction portions of the A-SET are decided as R₁ >>R₂ and C1>>C₂respectively;

FIG. 3 is a graphical representation showing the I-V_(g) (Coulomboscillation) characteristics of the A-SET when V_(SD) is fixed to V_(b)shown in FIG. 2;

FIG. 4 is a circuit diagram showing the SET structure related to thesecond embodiment of the present invention;

FIG. 5 is a circuit diagram showing the SET structure related to thethird embodiment of the present invention;

FIG. 6 is a graphical representation showing the relationship betweenV_(g) and the number of charges stored on the island portions of twotunnel junction portions of the charge accumulation control circuit;

FIG. 7 is a graphical representation showing the conditions thatparameters related to the junction capacitances must be satisfied, whichare required when a one-input logic gate is constructed by the SET shownin FIG. 5;

FIG. 8 is a circuit diagram showing the single-electron logic devicestructure related to the fourth embodiment of the present invention;

FIG. 9 is a graphical representation showing the conditions thatparameters related to the junction capacitances must be satisfied, whichare required when a two-input logic gate is constructed by thesingle-electron logic device shown in FIG. 8;

FIG. 10 is a circuit diagram showing the single-electron logic devicestructure related to the fifth embodiment of the present invention;

FIG. 11(a) is a plane view showing the device structure of the A-SETrelated to the present invention shown in FIG. 1, and FIG. 11(b) is across-sectional view showing the same;

FIG. 12 is a plane view showing the device structure of thesingle-electron logic device related to the present invention shown inFIG. 5;

FIG. 13 is a plane view showing the device structure of thesingle-electron logic device related to the present invention shown inFIG. 5;

FIG. 14(a) is a cross-sectional view showing the device structure, takenalong the line A-A' in FIG. 13, and FIG. 14(b) is a cross-sectional viewshowing the same device structure, taken along the line B-B' in FIG. 13;

FIG. 15 is a circuit diagram showing the prior art single-electrontransistor having a capacitance-coupled gate;

FIG. 16 is a graphical representation showing the I-V_(SD)characteristics of the SET shown in FIG. 15, in which the gate bias istaken as a parameter; and

FIG. 17 is a graphical representation showing the I-V_(g)characteristics of the SET shown in FIG. 15, in which V_(SD) is fixed.

Embodiments

The embodiments of the present invention will be described hereinbelowwith reference to the attached drawings. FIG. 1 is a circuit diagramshowing a first embodiment of the single-electron transistor accordingto the present invention. In the drawing, two capacitors 1 and 2 havingcapacitances C₁ and C₂, respectively form a double-tunnel junctioncircuit as an active circuit, through which charge tunnelling can beenabled. The tunnel resistances thereof are R₁ and R₂, respectively.Here, however, these junction parameter values are assumed to bedetermined in the ranges in which a single-electron tunnelling can beexpected through the junctions and thereby the Coulomb blockade canoccur. For the purpose, the following conditions are required to besatisfied:

    min (e.sup.2 /2C.sub.1, e.sup.2 /2C.sub.2)≧k.sub.B T,(1)

    R.sub.i ≧R.sub.q, (i=1, 2),                         (2)

where e is the prime charge, k_(B) is the Boltzmann's constant, T isabsolute temperature, and R_(q) =h/(2e²)=12.9 kΩ is the quantumresistance.

As shown in FIG. 1, the two tunnel junction portions 1 and 2 areconnected in series to form a double-tunnel junction structure. The oneend thereof is a source electrode terminal 5 and the other end thereofis a drain electrode terminal 6, between which a voltage V_(SD) (=V_(S)-V_(D)) is applied. A region denoted by 4 between the two tunneljunction portions 1 and 2 corresponds to an island portion of thedouble-tunnel junction, which is connected to a gate electrode terminal7 via an ordinary capacitor 3 of a capacitance C_(g) (through which thetunnelling will not occur). This gate electrode terminal 7 is a signalinput terminal. The object of the present invention cannot be attainedby the current-voltage (I-V_(SD)) characteristics the same as those ofthe conventional single-electron transistor;. that is, the roughlylinear (I-V_(SD)) characteristics having a gap. In the double-tunneljunction structure as described above, however, there exist combinationsof junction parameters which can represent the step-like (I-V_(SD))characteristics (referred to as Coulomb staircase, hereinafter). Byutilizing the characteristics, it is possible to expect the object andeffect of the present invention.

In the double-tunnel junction structure, the Coulomb staircase resultsfrom the incremental charging on the island portion 4 by the appliedbias voltage V_(SD). Here, it should be noted that the charge will notbe accumulated on the island portion 4 by the application of the gatebias voltage V_(g). When the Coulomb staircase is developed, the chargeaccumulated on the island portion 4 is quantized to a roughly integralvalue times e (a prime charge). Therefore, it is necessary to determinethe junction parameters so that the charge can be accumulated on theisland portion 4. For this purpose, a certain difference is required inthe time constants R₁ ·C₁ and R₂ ·C₂ of the tunnel junction portions 1and 2, respectively. That is, the junction parameters are determined insuch a way that at least one of the two following conditions can besatisfied:

    R.sub.1 C.sub.1 >R.sub.2 C.sub.2 or R.sub.1 C.sub.1 <R.sub.2 C.sub.2.(3)

Of course, it is preferable that the difference in RC time constants ofjunctions is large. Preferably, the difference is determined so that onediffers from the other by at least one digit or more.

Further, in order to enhance the effect of incremental charging on theisland portion 4 by the applied bias voltage, the junction parametervalues should be chosen so that any of the two following conditions canbe satisfied:

    R.sub.1 >R.sub.2, C.sub.1 ≧C.sub.2                  (4)

    R.sub.2 >R.sub.1, C.sub.2 ≧C.sub.1                  (5)

In these conditional expressions, it is desirable that the differencebetween the two is large.

For simplification, on the assumption that the junction parameters areselected so as to satisfy the condition as defined by the equation (4),the transport properties and the effects of the asymmetricaldouble-tunnel junction single-electron transistor (A-SET) as shown inFIG. 1 will be explained hereinbelow. FIG. 2 shows the typical I-V_(SD)characteristics of the A-SET shown in FIG. 1, and FIG. 3 shows theI-V_(g) characteristics obtained when the gate bias voltage V_(g) of thesame A-SET is changed; that is, so-called Coulomb oscillation. As shownin FIG. 2, the I-V_(SD) characteristics represent the Coulomb staircaseaccording to the bias voltage V_(SD), and this indicates that thedouble-tunnel junction circuit constituting an active circuit involves acharge accumulation control circuit. In this case, as understood by FIG.3, the output current I changes in accordance with roughly a rectangularshape according to the gate voltage V_(g), and further the rectangularshape is repeated periodically. Accordingly, when the input voltageV_(g) is set to a voltage corresponding to the middle point of theroughly flat portion of the rectangular range, it is possible to obtaina stable output to the fluctuations of the input voltage V_(g). Further,by the unitization of the periodic characteristics thereof, it is alsopossible to set the two input levels at two different valuessufficiently separated from each other.

For instance, the larger current value is determined as the high leveloutput (H_(out)), and the middle point of the voltage rangecorresponding to H_(out) is determined as V_(H) as shown in FIG. 3. Onthe other hand, the smaller current value is determined as the low leveloutput (L_(out)), and the middle point of the voltage rangecorresponding to L_(out) is determined as V_(L) also as shown in FIG. 3.In this case, if both the middle voltages are selected as V_(H) <V_(L)and further if the vicinity of V_(H) is determined as the low levelinput L_(in) and the vicinity of V_(L) is determined as the high levelinput H_(in), the A-SET operates under these conditions as an inverter.Further, by use of the periodic characteristics of the Coulomboscillation (the oscillation period of this case is e/C₁), if both themiddle voltages are selected as V_(H) >V_(L), and further if thevicinity of V_(H) is set to the high level input H_(in) and the vicinityof V_(L) is set to the low level input L_(in), the A-SET can operateunder these conditions as an ordinary switching device. Further, asalready explained, it is also possible to set V_(H) and V_(L)sufficiently away from each other owing to the presence of the periodiccharacteristics.

Here, the single-electron transistor whose basic structure is such thatthe two tunnel junction structures are connected in series has beendescribed. In more generic way, the same as above can be applied to thesingle-electron tunnelling logic device of a multi-tunnel junctionstructure composed of a series of single-electron tunnel junctions (inwhich a plurality of tunnel junction structures are connected inseries).

FIG. 4 shows a single-electron transistor related to a second embodimentaccording to the present invention. In FIG. 4, the double-tunneljunction circuit constituting an active circuit is of symmetricaldouble-tunnel junction structure, in which the reference numerals 8 and9 denote tunnel junction portions; 10 denotes a source electrode; 11denotes a drain electrode; and 12 denotes an island portion. Here, thejunction parameters of the tunnel junction portions 8 and 9 aredetermined symmetrically, so that no Coulomb staircase is obtained, inthe same way as with the case of the conventional one.

To the island portion 12, a charge accumulation control circuit isconnected via an ordinary capacitor 17 (through which no tunnellingoccurs). The charge accumulation control circuit is composed of a tunneljunction portion 13 and an impedance circuit (ZC) 14 both connected inseries. The capacitor 17 is connected to a middle electrode (island)portion 16 of this series-connected control circuit. One end (on thetunnel junction portion (13) side) of the control circuit is a gateelectrode 15 to which a signal to be quantized is inputted. Therefore, aquantized charge is accumulated on the island portion 16 of the chargeaccumulation control circuit. In other words, charges roughly equal toan integral value times e (prime charge) are stored on the island 16with a voltage range according to the voltage for driving thedouble-tunnel junction, and the potential at this island portion 12 canbe controlled by this charge. This indicates that in the case of theconstruction as shown in FIG. 4, a roughly constant output current I canbe obtained over a voltage range according to an input voltage V_(g), sothat it is possible to design a device having a margin for the inputsignal. As this impedance circuit ZC, any circuits can be adopted, asfar as the circuit has such a function as to charge electrons in unit ofsingle electron at the middle electrode 16. For instance, a circuitincluding a single-electron tunnel junction structure or asingle-electron transistor can be adopted and it is permissible to usewithout the impedance circuit ZC itself. Further, a circuit providedwith a multiple single-electron tunnel junction train having two or moretunnel junction portions and with a terminal group led out of therespective island portions between two adjacent tunnel junctions via acapacitance element, respectively can be adopted. Further, a simpleordinary capacitance train can be considered. In any cases, when thecapacitance of the circuit 14 is determined to be a value about 10 timeslarger than that of the junction capacitance C13 of the tunnel junctionportion 13, it is possible to obtain a sufficient margin to the inputsignal. For instance, if C₁₃ is 10 aF, the circuit 14 having acapacitance of about 100 aF is used.

FIG. 5 shows a third embodiment of the present invention, in which theimpedance circuit 14 shown in FIG. 4 is formed by the tunnel junctionstructure. In FIG. 5, a double-tunnel junction circuit composed of twotunnel junction portions 13 and 18 constructs the charge accumulationcontrol circuit. An island portion 16 of this charge accumulationcontrol circuit is connected to another island portion 12 between thetwo tunnel junction portions 8 and 9 via a capacitor 17 having acapacitance C_(g). The capacitances of the tunnel junction portions 8,9, 13 and 18 are C₈, C₉, C₁₃ and C₁₈, respectively, and the tunnelresistances thereof are R₈, R₉, R₁₃ and R₁₈, respectively.

A drain electrode 11 of the active circuit is grounded; a sourceelectrode 10 thereof is connected to an output terminal 10 foroutputting an output voltage V_(out) ; and a load element 20 of aresistance R₁ is connected to the output terminal 10. The other end ofthis load element 20 is connected to a bias voltage application terminal21 for supplying a bias voltage V_(b) required to drive the transistor.

An electrode of the tunnel junction portion (13) side of the chargeaccumulation control circuit is a gate electrode 22 for inputting avoltage signal V_(g) to be quantized to the transistor. An electrode 23of the tunnel junction portion (18) side of the same charge accumulationcontrol circuit is grounded.

The transistor as described above is assumed to be operative under suchenvironments that the Coulomb blockade occurs. For the purpose, therespective composing elements must satisfy the following conditions, forinstance: ##EQU1##

    R.sub.j ≧R.sub.q (j=8, 9, 13, 18)                   (7)

where e is the prime charge, k_(B) is the Boltzmann's constant, T is theabsolute temperature, and R_(q) =h/(2e²)=12.9 kΩ is the quantumresistance. Further, C.sub.Σ.sup.(i) (i=1, 2) are the capacitances ofthe island portions 12 and 16 of the two double-tunnel junctioncircuits, respectively, which can be expressed as

    C.sub.Σ.sup.(1) =C.sub.g +C.sub.8 +C.sub.9, C.sub.Σ.sup.(2) =C.sub.g +C.sub.13 +C.sub.18.

In the double-tunnel junction circuit for constituting the activecircuit, the resistance R, of the load element 20 is determined to be atleast higher than that of the quantum resistance R_(q) so that thecircuit can be operative under the high impedance environment asfollows:

    R.sub.1 ≧R.sub.q                                    (8)

Further, the double-tunnel junction circuit is constructed by suchjunction parameters that the stepwise-changing I-V_(SD) characteristics(referred to as Coulomb staircase) cannot be developed. For this, thejunction parameters are determined as

    R.sub.8 ≧R.sub.9, C.sub.8 ≧C.sub.9           (9)

or

    R.sub.8 ≦R.sub.9, C.sub.8 ≧C.sub.9           (10)

On the other hand, in the double-tunnel junction circuit of the chargeaccumulation control circuit, the resistance components of theelectrodes connected thereto are determined to be sufficiently smallerthan that of the quantum resistance R_(q) so that the circuit can beoperative under the low impedance environment.

Further, the double-tunnel junction circuit is constructed byasymmetrical junction parameters so that the stepwise-change I-V_(SD)characteristics (referred to as Coulomb staircase) can be developed. Inthis case, the conditions that the Coulomb staircase is obtained in thedouble-tunnel junction circuit are as follows:

    R.sub.13 >R.sub.18, C.sub.13 ≧C.sub.18              (11)

or

    R.sub.13 <R.sub.18, C.sub.13 ≦C.sub.18              (12)

Where the above-mentioned conditions are satisfied, when the voltageV_(g) is applied to the gate electrode 22 of the double-tunnel junctioncircuit, tunnel current will not flow in the range of .linevertsplit.V_(g) .linevert split.<V_(c) because tunnelling is inhibited. Thevoltage V_(c) at this critical point is referred to as Coulomb blockadevoltage. On the other hand, in the range of .linevert split.V_(g).linevert split.≧V_(c), the tunnel current increases stepwise withincreasing applied voltage, so that the Coulomb staircase develops. Thisphenomenon results from the fact that the charge stored on the islandportion 16 of the double-tunnel junction circuit is quantized in unit ofthe prime charge e under the Coulomb blockade conditions. In otherwords, the charge stored on the island portion 16 changes by±e withincreasing applied voltage V_(g). Here, the sings±of the prime charge eare determined in dependence upon the junction parameters of thedouble-tunnel structure.

For simplification, only the case where the conditions as expressed bythe equation (12) are satisfied will be discussed hereinbelow. In thiscase, the Coulomb blockade voltage becomes V_(c) =e/(2C₁₈). In general,although the voltage step ΔV₂ of the Coulomb staircase depends upon thejunction parameters of the tunnel junction portions 13 and 18 or thetemperature, as far as the temperature satisfies the equation (6)sufficiently and further the tunnel resistances of the double-tunneljunctions are different from each other extremely as R₁₈ >>R₁₃, thevoltage step ΔV₂ of the Coulomb staircase can be given approximately as

    ΔV.sub.2 =e/C.sub.18.                                (13)

In FIG. 6, the charge n₂ accumulated on the island portion 16 of thedouble-tunnel junction circuit of the charge accumulation controlcircuit is expressed in unit of the prime charge e to the signal voltageV_(g). Therefore, in this case, the following charge can be induced inthe capacitance 17:

    Q.sub.g =(C.sub.g /C.sub.Σ.sup.(2))e·n.sub.2.(14)

Now, since the active circuit is operative under the high impedanceenvironment, the Coulomb blockade voltage V_(c1) can be expressed as

    V.sub.c1 =e/(2C.sub.1),                                    (15)

where C₁ denotes the series-connected capacitance of the capacitors C₈and C₉ of the two tunnel junction portions 8 and 9 expressed as follows:

    C.sub.1 =C.sub.8 ·C.sub.9 /(C.sub.8 +C.sub.9).    (16)

Therefore, when the bias voltage V_(b) is applied to the voltageapplication terminal 21 so that the output voltage at the electrode 10becomes

    V.sub.out ≧V.sub.c1,                                (17)

the output voltage V_(out) changes in period the prime charge eaccording to Q_(g) given by the equation (14). In the ideal case, theoutput voltage V_(out) becomes as ##EQU2## where

    δV=e/C.sub.Σ.sup.(1),                          (19)

    x=Q.sub.q2 /e-[Q.sub.q2 /e+0.5].                           (20)

Here, [a] indicates the greatest integer less than or equal to a.

By the way, since x lies within a range of 0.5≦x<0.5 according to Q_(g),V_(out) is minimum when x=-1/2, increases with increasing x, and reachesits maximum value when x=1/2-O⁺. Therefore, by appropriately selectingx_(L) and x_(H) in the ranges (-0.5<x_(L) <0) and (0<x_(H) <0.5),respectively, it is possible to allow the output belonging to the rangeof (-0.5≦x≦x_(L)) to correspond to the "low-level" signal and the outputbelonging to the range of (x_(H) ≦x≦0.5) to correspond to the"high-level" signal, respectively. However, it is necessary to selectthe junction parameters in such a way that the output rangescorresponding to (-0.5≦x≦x_(L)) and (x_(H) ≦x≦0.5) can stay within thevoltage step ΔV₂ of the Coulomb staircase as given by the equation (13).

Further, in the following discussion, the generic characteristics can bemaintained if V_(b) and R₁ are rewritten as

    V.sub.b =V.sub.c1 +α·δV, R.sub.1 =γ·(R.sub.13 +R.sub.18).                   (21)

On the basis of the conditions of equations (7) and (8), γ is requiredto satisfy

    γ≧1/2.                                        (22)

Further, it is understood that on the basis of the condition of theequation (17), it is sufficient if α=γ. Under these conditions, theequation (18) can be rewritten as

    V.sub.out =V.sub.c1 +(γ/(γ+1)·(1+2x)δV.(23)

By substituting x=-1/2 and x=x_(L) into the equation (23), the lowerlimit value V_(L).sup.(inf) and the upper limit value V_(L).sup.(sup) ofthe low level signal V_(L) can be determined as

    V.sub.L.sup.(inf) =V.sub.c1

    V.sub.L.sup.(sup) V.sub.c1 +(γ/(γ+1))·(1+2x.sub.L)δV.     (24)

Further, by substituting x=x_(H), and x=1/2 into the equation (23), thelower limit value V_(H).sup.(inf) and the upper limit valueV_(H).sup.(sup) of the high level signal V_(H) can be determined as

    V.sub.H.sup.(inf) =V.sub.c1 +(γ/(γ+1))·(1+2x.sub.H)δV.

    V.sub.H.sup.(sup) =V.sub.c1 +(2γ/(γ+1))·δV.(25)

The input to the charge accumulation control circuit will be describedhereinbelow.

                  TABLE 1                                                         ______________________________________                                        Q.sub.g /e C.sub.g C.sub.Σ .sup.(2) · n.sub.2                                         C.sub.g /C.sub.Σ .sup.(2) · n.sub.2                            '                                                      ______________________________________                                        x          X (C.sub.g /C.sub.Σ .sup.(2) · n.sub.2)                                    X (C.sub.g /C.sub.Σ .sup.(2) ·                                 n.sub.2 ')                                             ______________________________________                                    

Here, in Table 1, the values x to Q_(g) are listed. Further, thefunction X(y) is defined as X(y)=y-[y+1/2], where [a] denotes thegreatest integer less than or equal to a.

Table 1 above lists the values Q_(g) given by the equation (14) andvalues x given by the equation (20) when the charge stored on the islandportion 16 of the charge accumulation control circuit is (n₂ ·e) or (n₂'·e), respectively. According to FIG. 6 in order to obtain the abovecharged states in the island portion 16, the following voltage V₂ isinputted to the gate electrode 22 of the charge accumulation controlcircuit:

    ΔV.sub.2 ·(n.sub.2 -(1/2))<V.sub.2 <ΔV.sub.2 ·(n.sub.2 +(1/2)) or

    ΔV.sub.2 ·(n.sub.2 '-(1/2))<V.sub.2 <ΔV.sub.2 ·(n.sub.2 '+(1/2)),

where n₂ and n₂ ' are integral values, respectively.

In accordance with these equations, the voltage characterized by n₂ isallowed to correspond to the "low-level (V_(L))" and the voltagecharacterized by n₂ ' is allowed to correspond to the "high-level(V_(H))". By substituting the equation (13) into the above equations,the following equations can be obtained:

    (e/C.sub.18)(n.sub.2 -(1/2))<V.sub.L <(e/C.sub.18)(n.sub.2 +(1/2)),(26)

    (e/C.sub.18)(n.sub.2 '-(1/2))<V.sub.H <(e/C.sub.18)(n.sub.2 '+(1/2)).(27)

On the basis of the relationship between the equations (26) and (27) andthe equations (24) and (25), respectively, the following equations canbe obtained

    V.sub.L.sup.(sup) ≦(e/C.sub.18)(n+(1/2),            (28)

    V.sub.L.sup.(sup) -V.sub.H.sup.(inf) <e/C.sub.18,          (29)

    V.sub.H.sup.(inf) ≧(e/C.sub.18 (n'-(1/2),           (30)

    V.sub.L.sup.(sup) -V.sub.H.sup.(inf) <e/C.sub.18,          (31)

where n₂ and n₂ ' are rewritten as n and n', respectively.

In practice, a logical gate in which the following equations aresatisfied is taken into account:

    C.sub.13 =(5-3β)C.sub.g,

    C.sub.18 =3(2+β)C.sub.g,                              (32)

    (C.sub.8 /C.sub.g)+(C.sub.9 +C.sub.g)=2p,

    (C.sub.8 /C.sub.g)·(C.sub.9 /C.sub.g)=q, (p,q>0)  (33)

    n'=n+3, n=5, 17, 29, . . .                                 (34)

Here, the situation that the equation (12) can be established isconsidered β must lie within a range as

    (-1/6)≦β<(5/3).

Under these conditions, since C_(g) /C.sub.Σ.sup.(2) =1/12, Table 1 canbe rewritten as

                  TABLE 2                                                         ______________________________________                                        Q.sub.g /e    n.sub.2 /12                                                                          (n.sub.2 + 3)/12                                         ______________________________________                                        x             10/24  -8/24                                                    ______________________________________                                    

Table 2 lists the values x to Q_(g).

Here, x_(L) and x_(H) are selected as

    X.sub.L =-7/24, X.sub.H =9/24                              (36)

Further, when the equations (28) to (31) are evaluated by substitutingthe equation (36) into the equations (24) and (25) and by use of theequations (15), (16), (32) and (33), the following conditional equationswith respect to p and q are obtained as ##EQU3##

Therefore, when β, γ, p, q and n (=5, 12, 29, . . . ) are selected sothat the above-mentioned conditions and the equation (22) can besatisfied and further when the V_(L) and V_(H) given by the equation(26) and (27) are allowed to correspond to the high level (H) and thelow level (L) of the input and output signals, the input and outputlevels of the transistor as shown in FIG. 5 can be given by thefollowing table 3:

                  TABLE 3                                                         ______________________________________                                        INPUT V.sub.g      L     H                                                    ______________________________________                                        OUTPUT V.sub.out   H     L                                                    ______________________________________                                    

Table 3 lists the input and output levels of the single-electrondouble-tunnel junction logic gate of the third embodiment of the presentinvention shown in FIG. 5. As a result, the single-electrondouble-tunnel junction device as constructed above can operate as aninverter.

Here, when β, γ and n are determined in practice as β=1.5; γ=10; andn=5, p and q which satisfy the equations (37) to (39) lie within a rangeas shown by oblique lines in FIG. 7. For instance, p=2.5 and q=5.5 liewithin the oblique-line range. When β, γ, p, q and n are determined asdescribed above, on the basis of the equations (32) and (33), thecapacitances of the tunnel junctions can be determined as

    C.sub.8 ≈1.6C.sub.g ; C.sub.9 ≈3.4C.sub.g,

    (or C.sub.13 ≈3.4C.sub.g ; C.sub.18 ≈1.6C.sub.g),

    C.sub.13 =C.sub.g /2; C.sub.18 =21C.sub.g /2.

Here, C_(g) is determine so as to satisfy the equation (6). On the otherhand, the tunnel resistances of the tunnel junctions are selected sothat the equations (9) (or (10)), (12) and (7) can be satisfied.

When the junction parameters are decided as described above, thetransistor of the third embodiment can operate as an inverter.

According to the present embodiment, the junction parameters of thecharge accumulation control circuit are so determined as to develop theCoulomb staircase, and further the current I flowing through the activecircuit (i.e., the output voltage V_(out)) is kept constant with respectto the input voltage V_(g) within a predetermined range, on the basis ofthe staircase characteristics between the input voltage V_(g) and thecharge n₂ stored on the island portion. Accordingly, it is possible toobtain such an effect that the input margin can be improved.

FIG. 8 shows a fourth embodiment of the single-electron tunnel junctionlogic device according to the present invention, which functions as atwo-input device. The device is composed of a double-tunnel junctioncircuit (8 and 9) which functions as an active circuit without havingthe Coulomb staircase characteristics in the I-V_(SD) characteristiccurve and two double-tunnel junction circuits which function as thecharge accumulation control circuit having Coulomb staircasecharacteristics.

One end of the tunnel junction portion 13 is a gate electrode (i.e., aninput terminal) 22 to which a signal voltage V_(g1) is applied, and oneend of the tunnel junction portion 18 is an electrode 23 that isgrounded. Further, one end of a capacitor 17 with the capacitance C_(g1)is connected to the island portion 16 between the two tunnel junctionportions 13 and 18 and the other end thereof is connected to an islandportion 12 of the active circuit.

The second charge accumulation circuit is composed of the thirddouble-tunnel junction circuit (a series-circuit of two tunnel junctionportions 131 and 181). In FIG. 8, C₁₃₁ is the capacitance of tunneljunction portion 131, R₁₃₁ is the resistance of the tunnel junctionportion 131, C₁₈₁ is the capacitance of the tunnel junction portion 181,and R₁₈₁ is the resistance of the tunnel junction portion 181. Oneelectrode of the tunnel junction portion 131 is a signal voltage inputterminal V_(g2), and one electrode of the tunnel junction portion 181 isgrounded. One end of a capacitor 171 having a capacitance C_(g2) isconnected to the island portion 162 between the two tunnel junctionportions 131 and 181, and the other end thereof is connected to theisland portion 12 of the active circuit.

The transistor constructed as described above is assumed to be operativeunder the environment that the Coulomb blockade develops. For thispurpose, the respective composing devices st satisfy the followingconditions, for instance: ##EQU4##

    R.sub.j >R.sub.q, (j=8,9,13,18,131,181)                    (41)

Here, C.sub.Σ.sup.(i) (i= 1, 2, 3) denotes each capacitance of themiddle electrodes of the three double-tunnel junction structures,respectively, which can be expressed as

    C.sub.Σ.sup.(1) =C.sub.g1 +C.sub.g2 +C.sub.8 +C.sub.9,

    C.sub.Σ.sup.(2) =C.sub.g1 +C.sub.13 +C.sub.18,

    C.sub.Σ.sup.(3) =C.sub.g2 +C.sub.g131 +C.sub.181,

Further, in the same way as with the case of the third embodiment, theresistance R₁ of the load element 20 is determined so that the activecircuit can be operative under the high impedance environment, that is,the condition as expressed by the equation (8) can be satisfied. On theother hand, in the double-tunnel junction circuits for constructing thecharge accumulation control circuits, the resistance components of theelectrodes connected thereto are determined to be sufficiently smallerthan the quantum resistance R_(q), so that the circuit can be operativeunder the low impedance environment.

In addition to the above-mentioned conditions, the active circuit isconstructed by the junction parameters for satisfying the equations (9)and (10) so that the Coulomb staircase is not developed in thecurrent-voltage characteristics. On the other hand, the double-tunneljunctions for constituting the charge accumulation control circuits areconstructed by asymmetrical junction parameters, so that the Coulombstaircase can be developed in the current-voltage characteristics, asfollows:

    R.sub.13 >R.sub.18, C.sub.13 ≧C.sub.18 (in tunnel junctions 13 and 18),

    R.sub.131 >R.sub.181, C.sub.131 ≧C.sub.181 (in tunnel junctions 131 and 181)                                                  (42)

    or

    R.sub.13 >R.sub.18, C.sub.13 ≦C.sub.18 (in tunnel junctions 13 and 18),

    R.sub.131 <R.sub.181, C.sub.131 ≦C.sub.181 (in tunnel junctions 131 and 181)                                                  (43).

Under the conditions that the equations (42) and (43) are bothsatisfied, when voltages are applied to the gate electrodes 22 and 221of the charge accumulation control circuits, if the absolute values|V_(g1) | and |V_(g2) | are lower than the Coulomb blockade voltagesV_(c2) and V_(c3) respectively, the tunnelling is suppressed and notunnel current flows therethrough. On the other hand, in the range wherethe absolute values |V_(g1) | and |V_(g2) | are higher than the Coulombblockade voltages V_(c2) and V_(c3), respectively, the Coulomb staircasecan be developed. For simplification, the case where the equation (43)is satisfied will be considered. In this case, the Coulomb blockadevoltage becomes V_(c2) =e/(2C₁₈) and V_(c3) =e/(2C₁₈₁). In general,although the voltage steps ΔV₂ and ΔV₃ of the Coulomb staircase dependupon the junction parameters or the temperature, when the temperaturesatisfies the equation (40) sufficiently and further when the tunnelresistances of the double-tunnel junctions are different from each otherextremely as R₁₈ >>R₁₃ and R₁₈₁ >>R₁₃₁, the voltage steps ΔV₂ and ΔV₃ ofthe Coulomb staircase can be given approximately as

    ΔV.sub.2 =e/C.sub.18

    ΔV.sub.3 =e/C.sub.181                                (44)

Here, the charge n₂ or n₃ accumulated on the island portion 16 or 162 ofeach of the respective double-tunnel junction circuits is quantizedaccording to the applied voltage V_(g1) or V_(g2), as shown in FIG. 6.In this case, the following charges can be induced in the capacitors 17and 171, respectively:

    Q.sub.g2 =(C.sub.g1 /C.sub.Σ.sup.(2))e·n.sub.2,

    Q.sub.g2 =(C.sub.g2 /C.sub.Σ.sup.(3))e·n.sub.3.(45)

Therefore, when an appropriate bias voltage V_(b) is applied to thevoltage application terminal 21 so that the conditions as expressed bythe equation (17) can be satisfied, in the ideal case, V_(out) becomesas expressed by the equation (18). Here, however, x is expressed as##EQU5## where [a] is the greatest integer less than or equal to a.

Therefore, V_(out) changes periodically in unit of the prime charge eaccording to an addition of Q_(g1) and Q_(g2) in the equation (46). Asalready explained in the third embodiment shown in FIG. 5, when x_(L)and x_(H) are determined appropriately, it is possible to allow theoutput within the range of (-0.5≦x≦x_(L)) to correspond to the"low-level" signal and the output within the range of (x_(H) ≦x≦0.5) tocorrespond to the "high-level" signal, respectively. However, it isnecessary to select the junction parameters in such a way that theoutput ranges can stay within the voltage step of Coulomb staircase ΔV₂or ΔV₃ as given by the equation (44).

Here, in the same way as with the case of the third embodiment, V_(b)and R₁ are rewritten as the equation (21). On the basis of theconditions as expressed by the equations (8), (41) and (17), it issufficient that α=γ and γ is determined as expressed by the equation(22). In this case, V_(out) can be rewritten as the equation (23), sothat the upper and lower limits of the low-level signal and thehigh-level signal can be determined as expressed by the equations (24)and (25).

Here, for simplification, the following case will be considered:

    C.sub.g1 =C.sub.g2 =C.sub.g, C.sub.131 =C.sub.13, and C.sub.181 =C.sub.18.(47)

                  TABLE 4                                                         ______________________________________                                        Q.sub.g2 /e\Q.sub.g1 /e                                                         C.sub.g1 /C.sub.Σ .sup.(2) · n.sub.2                                         C.sub.g1 /C.sub.Σ .sup.(2) ·                                   n.sub.2 '                                           ______________________________________                                        C.sub.g2 /C.sub.Σ .sup.(3) · n.sub.3                                       X(C.sub.g1 /C.sub.Σ .sup.(2) · n.sub.2                                       X(C.sub.g1 /C.sub.Σ .sup.(2) ·                                 n.sub.2 ' +                                                     C.sub.g2 /C.sub.Σ .sup.(3) · n.sub.3)                                        C.sub.g2 /C.sub.Σ .sup.(3) ·                                   n.sub.3)                                            C.sub.g2 /C.sub.Σ .sup.(3) · n.sub.2 '                                     X(C.sub.g1 /C.sub.Σ .sup.(2) · n.sub.2                                       X(C.sub.g1 /C.sub.Σ .sup.(2) ·                                 n.sub.2 ' +                                                     C.sub.g2 /C.sub.Σ .sup.(3) · n.sub.3 ')                                      C.sub.g2 /C.sub.Σ .sup.(3) ·                                   n.sub.3 ')                                          ______________________________________                                    

Table 4 lists the values x to Q_(g1) Q_(g2), respectively. Here, thefunction X(y) is defined as X(y)=y-[y+1/2], where [y+1/2] denotes thegreatest integer less than or equal to (y+1/2).

In more detail, Table 4 above indicates the values x given by theequation (46) when the charges stored on the island portions 16 and 162of the second and third double-tunnel junction circuits for constitutingthe charge accumulation control circuit are (n₂ ·e, n₃ ·e) or (n₂ '·e,n₃ ', e) respectively.

According to FIG. 6. in order to obtain the charges stored on the islandportions as described above, the following voltages V₂ and V₃ areinputted to the gate electrodes 22 and 221 of the second and thirddouble-tunnel junction circuits, respectively:

    ΔV2·(n.sub.2 -(1/2))<V.sub.2 <ΔV.sub.2 ·(n.sub.2 +(1/2))

    ΔV.sub.3 ·(n.sub.3 -(1/2))<V.sub.3 <ΔV.sub.3 ·(n.sub.3 +(1/2))

    or

    ΔV2·(n.sub.2 '-(1/2))<V.sub.2 <ΔV.sub.2 ·(n.sub.2 '+(1/2))

    ΔV.sub.3 ·(n.sub.3 '-(1/2))<V.sub.3 <ΔV.sub.3 ·(n.sub.3 '+(1/2))

where n₂, and n₂ ', n₃, and n₃ ' are all an integer, respectively.

In accordance with these equations, the voltage corresponding to n₂ andn₃ are allowed to correspond to the "low-level" input signal and thevoltage corresponding to n₂ ' and n₃ ' are allowed to correspond to the"high-level" input signal. In this example, since the capacitances ofthe second and third double-tunnel junctions are equal to each other,ΔV₂ =ΔV₃. Therefore, in order to use the same-level input signals forthe second and third double-tunnel junction circuits, it is sufficientto choose as n₂ =n₃ =n and n₂ '=n₃ '=n. By substituting the equation(44) into the above equations, the above equations can be rewritten as:

    (e/C.sub.18)(n-(1/2))<V.sub.L <(e/C.sub.18)(n+(1/2)),      (48)

    (e/C.sub.18)(n'-(1/2))<V.sub.H <(e/C.sub.18)(n'+(1/2)).    (49)

On the basis of the relationship between the equations (48) and (49) andthe equations (24) and (25), respectively, the equations (28) to (31)similar to those of the third embodiment can be obtained.

In practice, a logical gate in which the following equations aresatisfied is taken into account:

    C.sub.131 =C.sub.13 =(11-3β)C.sub.g,

    C.sub.181 =C.sub.18 =3(4+β)C.sub.g,                   (50)

    (C.sub.8 /C.sub.g)+(C.sub.9 +C.sub.g)=2p,

    (C.sub.8 /C.sub.g)·(C.sub.9 /C.sub.g)=q(p,q>0),   (51)

    n'=n+3, n=5,29,53, . . .                                   (52)

Here, since the situation that the equation (43) is established isconsidered, β must lie within a range as

    (-1/6)≦β<(11/3)                                (53)

Under these conditions, since C_(g1) /C.sub.Σ.sup.(2) =C_(g2)/C.sub.Σ.sup.(3) =1/24,

Table 4 can be rewritten as

                  TABLE 5                                                         ______________________________________                                        Q.sub.g2 /e\Q.sub.g1 /e                                                             n/24    (n + 3)/24                                            ______________________________________                                        n/24             10/24  -11/24                                                (n + 3)/24      -11/24   -8/24                                                ______________________________________                                    

Table 5 lists the values x to Q_(g1) and Q_(g2).

Here, x_(L) and x_(H) are selected as

    x.sub.L =-7/24, x.sub.H =9/24.                             (54)

Further, when the equations (28) to (31) are evaluated by substitutingthe equation (54) into the equations (24) and (25) and by use of theequations (15), (16), (19), (50) and (51), the following conditionalequations with respect to p and q can be obtained as

    x.sub.L =-7/24, x.sub.H =9/24.                             (54)

Further, when the equations (28) to (31) are evaluated by substitutingthe equation (54) into the equations (24) and (25) and by use of theequations (15), (16), (19), (50) and (51), the following conditionalequations with respect to p and q can be obtained as ##EQU6##

Therefore, when β, γ, p, q and n (=5, 29, 53, . . . ) are selected sothat the above-mentioned conditions and the equation (22), (47) and (53)can be satisfied and further when the V_(L) and V_(H) given by theequation (48) and (49) are allowed to correspond to the high level (H)and the low level (L) of the input and output signals, respectively. Theinput and output levels of the device of the fourth embodiment as shownin FIG. 8 can be given by the following table 6:

                  TABLE 6                                                         ______________________________________                                        V.sub.g2 \V.sub.g1                                                                   L     H                                                      ______________________________________                                        L                H     L                                                      H                L     L                                                      ______________________________________                                    

Table 6 lists the input and output levels of the single-electrondouble-tunnel junction logic gate of the fourth embodiment of thepresent invention. Therefore, the single-electron double-tunnel junctiondevice as constructed above can operate as a NOR gate.

Here, when β, γ, p, q, and n are determined in practice as β=1.5; γ=10;and n=5, p and q which satisfy the equations (55) to (57) lie in a rangeas shown by oblique lines in FIG. 9. For instance, p=5 and q=24 liewithin the oblique-line range. When β, γ, p, q and n are determined asdescribed above, on the basis of the equations (50), (51) and (47), thecapacitances of the tunnel junctions can be determined as

    C.sub.8 =4C.sub.g, C.sub.9 =6C.sub.g

    (or C.sub.8 =6C.sub.g, C.sub.9 =4C.sub.g),

    C.sub.g1 =C.sub.g2 =C.sub.g,

    C.sub.131 =C.sub.13 -C.sub.g /2,

    C.sub.181 =C.sub.18 =45C.sub.g /2.

C_(g) is determined so as to satisfy the equation (40). On the otherhand, the tunnel resistances of the tunnel junctions are selected sothat the equations (9) (or (10)), (43) and (41) can be satisfied.

When the junction parameters of the single-electron tunnelling logicdevice are decided as described above, the logic device of thisembodiment can operate as a NOR gate. Further, when a circuit composedof the load element 20 and the output terminal 10 is connected to apoint 11 in FIG. 8, it is possible to operate this embodiment as an ORgate.

In the above-mentioned third embodiment, a one-input logic device hasbeen explained, and in the above-mentioned fourth embodiment, atwo-input logic device has been explained. Without being limitedthereto, the present invention can construct a multi-input logic device.In this case, to the island portion of the first double-tunnel junctioncircuit for constituting an active circuit of Ohmic characteristics, theisland portions of k-th (k=2, 3, . . . ) double-tunnel junction circuitsare connected via a capacitor, respectively, as shown in FIG. 10.

In FIG. 10, reference numerals 192 to 19k denote charge accumulationcontrol circuits constructed by the k-th (k=2, 3, . . . ) double-tunneljunction circuits of Coulomb staircase characteristics. Each of thesecharge accumulation control circuits 193 to 19k is the same inconstruction as the control circuit 192.

As already explained in the third and fourth embodiments, it is possibleto obtain a predetermined logical operation result between the inputvoltage signals V_(g1) to V_(g)(k-1) and the output signal V_(out), bysetting the tunnel junction capacitances C₈ and C₉ and the tunnelresistances R₈ and R₉ of the double-tunnel junction circuit constitutingthe active circuit of Ohmic characteristics, and further by setting thetunnel junction capacitances C₁₃₀, C₁₃₁, . . . C₁₃(k-2), C₁₈, C₁₈₁, . .. , C₁₈(k-2), and the tunnel resistances R₁₃₀, R₁₃₁, . . . , R₁₃(k-2)·and R₁₈, R₁₈₁, . . . , R₁₈(k-2) of the second to k-th double-tunneljunction circuits 192 to 19k, respectively.

Finally, the device structure and the manufacturing method of the firstembodiment according to the present invention will be describedhereinbelow with reference to the attached drawings.

FIGS. 11(a) and 11(b) show a device structure of the A-SET according tothe present invention.

First, as shown in FIG. 11(b), a high purity InAs layer 32 is formed byepitaxial growth on a semi-insulating bulk InAs substrate in accordancewith MBE or MOCVD method. Then, a Ga_(x) In_(1-x) As barrier layer 33having a thickness of about 6 to 10 nm and including impurity additiveis formed by epitaxial growth in accordance with MBE or MOCVD method.After that, an n-Ga_(x) In_(1-x) As layer 34 including Sn as donorimpurities is grown. Here, it is preferable that the mixed crystal ratiox of Ga_(x) In_(1-x) As is more than 0.5. Further, it is of coursepossible to use any donor types to the Ga_(x) In_(1-x) As other than Snas the impurities of the n-Ga_(x) In_(1-x) As layer 34. In thehetero-interface between the InAs layer 32 and the Ga_(x) In_(1-x) Aslayer 33 formed as described above, a two dimensional electron gassystem is formed.

After that, a first metallic gate electrode 35 as shown in FIG. 11(a) isformed on the upper portion of the n-Ga_(x) In_(1-x) As layer 34, andfurther a second gate electrode 37 and a third gate electrode 38 areformed via a silicon oxide film 36. Here, it is possible to first forman n-InAs layer doped by donor-type impurities such as Te on then-Ga_(x) In_(1-x) As layer 34 and then to form the first gate electrode35 thereon. Further, it is also possible to form the third gateelectrode 38 on a silicon oxide film formed on the second gate electrode37. In this case, there exists no problem even if the edges of the thirdgate electrodes 38 are overlapped with the second gate electrode 37.Further, another insulating film can be used, instead of the siliconoxide film.

Further, it is possible to form a fine line-shaped conductive channel bydepleting the two dimensional electron gas under control of the voltageapplied to the first gate electrode 35. Further, it is possible to formbarriers at the fine line-shaped conductive channel by controlling thevoltage applied to the second gate electrode 37. The formed barriersfunction as a tunnel junction, and the region surrounded therebycorresponds to the island portion. Further, the tunnel resistance andthe tunnel capacitance can be adjusted separately by controlling thevoltages applied between the two second gate electrodes 37,respectively. By this, it is also possible to set the junctionparameters thereof asymmetrically so that the Coulomb staircase can beobtained. Further, the third gate electrode 38 is provided to controlthe potential on the island portion, which corresponds to the gateelectrode 7 of the A-SET shown in FIG. 1.

In above, in order to form the hetero-interface, a combination of InAsand Ga_(x) In_(1-x) As has been explained. Without being limited onlythereto, various combinations, as GaAs and Al_(x) Ga_(1-x) As, etc., canbe used. Further, if the shape and the position of the first gateelectrode are changed, it is also possible to utilize an inversion layerof Si and/or SiO₂ system as the two dimensional electron gas system. Inaddition, the shapes and the arrangements of the first, second and thirdgate electrodes are not limited to only those shown in FIG. 11(a). Thatis, as far as the fine line-shaped conductive channel and the tunnelbarriers at a part of the channel can be formed, gate electrodes of anyshape and arrangement can be used. For instance, the second and thirdgate electrodes of split type can be used in the same Way as with thecase of the first gate electrode. Further, in the above-mentionedembodiment, although the tunnel capacitances and resistances of thetunnel junction are controlled through the gate electrodes, withoutbeing limited only thereto, it is possible to previously determine therespective tunnel junction parameters so that the double-tunnel junctionbecomes asymmetrical. For instance, it is possible to from theasymmetrical double-tunnel junction in such a structure as "metal-tunnelinsulating film-metal".

The fourth embodiment can be manufactured in the same way as above onthe basis of the shape and arrangement of the gate electrodes as shownin FIG. 12. Here, however, the method of manufacturing the fourthembodiment through planar process will be described hereinbelow withreference to FIG. 13 and FIGS. 14(a) and (b). FIG. 13 is a plane viewshowing the fourth embodiment from above, and FIGS. 14(a) and (b) arecross-sectional views taken along the lines A-A' and B-B' in FIG. 13,respectively. Here, although not visible in practice, the portions 411and 412 are shown in FIG. 14(a) and the portions 45 and 46 are shown inFIG. 14(b) for convenience.

First, after a metallic film is deposited on an insulating substrate 41,a resist is formed. The resist is exposed to a light or an electron beamto leave only fine line-shaped resist thereon. Further, a fineline-shaped metallic range 42 is formed by etching process. Aninsulating film 43 is formed all over the surface thereof. In order tomake tunnel junction portions 44, a part of the formed insulating film43 is bored and thinned at a position over the fine line-shaped metallicwire 42 by use of an electron beam or a focused ion beam. The area ofthe bore is 0.01 μm² or preferably less than this value. Further, twoelectrode wiring layers 45 and 46 are formed so as to cover these tunneljunction portions 44. After that, an insulating film 47 is deposited allover the surface thereof. By the above-mentioned process, onedouble-tunnel junction can be manufactured, and the fine line-shapedmetallic region 42 becomes the island portion of the double-tunneljunction structure. The junction parameters such as the capacitance andresistance of the tunnel junction can be controlled by changing the sizeof the bore 44 at the tunnel junction portion and the film thicknessthereof. After a metallic film has been deposited on the insulating film47, a fine line-shaped metallic region 48 is formed between the alreadyformed electrode wiring layers 45 and 46 by the etching processing inthe direction different from the fine line-shaped metallic region 42, inthe same method as with the case of the fine line-shaped metallic region42. After that, the same process as with the case of the insulating film43, the tunnel-junction portion 44, the electrode wiring layers 45 and46 and the insulating film 47 is repeated. Further, an insulating film49 is deposited; a tunnel junction portion 410; two electrode wiringlayers 411 and 412 are formed; and an insulating film 413 is deposited.By the above-mentioned process, the second double-tunnel junctionstructure can be formed, and the fine line-shaped metallic region 48becomes the island portion of the second double-tunnel junction. Herethe junction parameters of the tunnel junction can be of coursecontrolled to any desired values on the basis of the size of the boreformed in the tunnel junction portion 410 and the film thicknessthereof. Two double-tunnel junction structures manufactured as describedabove are coupled capacitively each other between the two islandportions thereof via the insulating film 47. The capacitancetherebetween can be controlled by changing the thickness of theinsulating film between the two electrode wiring layers 45 and 46.

Effect of the Invention

As described above, according to the present invention, since the chargeaccumulated on the island portion is controlled in such a way that thecharacteristics between the output voltage and the input voltage to thegate circuit represent the Coulomb staircase, it is possible to obtainsquare (Coulomb oscillation) characteristics between the input signalvoltage and the output current, so that a constant output current valuecan be obtained belonging to a voltage range with constant width inputsignals. As a result, it is possible to increase the margin of thevoltage value corresponding to the respective input logical levels.Therefore, it is possible to obtain a stable output according to thefluctuations of the input level signal by the effective utilization ofthe double-tunnel junction characteristics.

Further, even when the output current values corresponding to the high-and low-level outputs in the Coulomb oscillation characteristics arechanged respectively, since the input voltage width can be maintained ata constant value, it is possible to widen the difference between thehigh- and low-level outputs, without reducing the voltage margin to theinput logical level.

What is claimed is:
 1. A single-electron tunnelling logic device,comprising:a double-tunnel junction portion formed by connecting firstand second single-electron tunnel junctions in series, a bias voltagebeing applied to both ends thereof; and a signal input portion connectedto a common junction portion between said first and secondsingle-electron tunnel junction portions via a capacitance element,wherein charge accumulated at the common junction portion is quantizedapproximately in integer-time unit of a prime charge according to thebias voltage;wherein in said double-tunnel junction portion, a tunnelresistance R_(T).sup.(i) and a junction capacitance C_(i) of the i-th(i=1, 2) single-electron tunnel junction are so determined that any oneof the following conditions can be satisfied:

    R.sub.T.sup.(1) >R.sub.T.sup.(2), C.sub.1 ≧C.sub.2, (i)

    R.sub.T.sup.(2) >R.sub.T.sup.(1), C.sub.2 ≧C.sub.1  (ii).


2. A single-electron tunnelling logic device, comprising:a double-tunneljunction portion formed by connecting first and second single-electrontunnel junctions in series, a bias voltage being applied to both endsthereof; and a signal input portion, connected to a common junctionportion between said first and second single-electron tunnel junctionportions via a capacitance element, wherein charge accumulated atanother common junction portion between said signal input portion andthe capacitance element is quantized approximately in integer-time unitof a prime charge according to an input voltage applied to said signalinput portion;wherein said signal input portion is a circuit formed byconnecting first and second impedance elements in series, and furtherthe common junction portion between the first and second impedanceelements is connected to the capacitance element.
 3. The single-electrontunnelling logic device of claim 2, wherein at least one of the firstand second impedance elements is formed by a single-electron tunneljunction.
 4. The single-electron tunnelling logic device of claim 3,wherein the first and second impedance elements are both formed by asingle-electron tunnel junction, respectively, and these twosingle-electron tunnel junctions are different from each other in atleast one of tunnel resistance and junction capacitance thereof.
 5. Asingle-electron tunnelling logic device, comprising:a double-tunneljunction portion formed by connecting first and second single-electrontunnel junctions in series, a bias voltage being applied to both endsthereof; and a signal input portion, connected to a common junctionportion between said first and second single-electron tunnel junctionportions via a capacitance element, wherein charge accumulated atanother common junction portion between said signal input portion andthe capacitance element is quantized approximately in integer-time unitof a prime charge according to an input voltage applied to said signalinput portion;wherein a plurality of the capacitance elements and aplurality of said signal input portions are connected to the commonjunction portion between said first and second single-electron tunneljunctions.
 6. The single-electron tunnelling logic device of claim 4,wherein a tunnel resistance R_(T).sup.(1) of the first impedance elementand a junction capacitance C₁ of the first impedance element and atunnel resistance R_(T).sup.(2) of the second impedance element and ajunction capacitance C₂ of the second impedance element are sodetermined that any one of the following conditions can be satisfied:

    R.sub.T.sup.(1) C.sub.1 >R.sub.T.sup.(2) C.sub.2,          (i)

    R.sub.T.sup.(1) C.sub.1 <R.sub.T.sup.(2) C.sub.2           (ii).


7. The single-electron tunnelling logic device of claim 6, wherein anyone of the following conditions can be satisfied:

    R.sub.T.sup.(1) >R.sub.T.sup.(2), C.sub.1 ≧C.sub.2, (i)

    R.sub.T.sup.(1) <R.sub.T.sup.(2), C.sub.1 ≦C.sub.2  (ii).